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71M6545/71M6545H Data Sheet
PDS_6545_009
The residual phase error is negligible, and is typically less than ±1.5 milli-degrees at 100Hz, thus it does
not contribute to errors in the energy measurements.
When using remote sensors, the CE performs the same delay compensation described above to align
each voltage sample with its corresponding current sample. Even though the remote current samples do
not pass through the 71M6545/H multiplexer, their timing relationship to their corresponding voltages is
fixed and precisely known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as
shown in Table 1 . Note that these slot assignments result in VA, VB and VC occupying multiplexer slots
3, 4 and 5, respectively (see Figure 4 ).
2.2.4
ADC Pre-Amplifier
The ADC pre-amplifier is a low-noise differential amplifier with a fixed gain of 8 available only on the
IADC0-IADC1 sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 ( I/O RAM 0x2704[5] ). When
disabled, the supply current of the pre-amplifier is <10 nA and the gain is unity. With proper settings of
the PRE_E and DIFF0_E ( I/O RAM 0x210C[4] ) bits, the pre-amplifier can be used whether differential
mode is selected or not. For best performance, the differential mode is recommended. In order to save
power, the bias current of the pre-amplifier and ADC is adjusted according to the ADC_DIV control bit ( I/O
RAM 0x2200[5] ).
2.2.5
A/D Converter (ADC)
A single 2 nd order sigma-delta A/D converter digitizes the voltage and current inputs to the device. The
resolution of the ADC, including the sign bit, is 21 bits ( FIR_LEN[1:0] = 01, I/O RAM 0x210C[2:1] ), or 22
bits ( FIR_LEN[1:0] = 10). The ADC is clocked by CKADC.
Initiation of each ADC conversion is controlled by the internal MUX_CTRL circuit as described earlier. At
the end of each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by
the multiplexer selection.
2.2.6
FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.
The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each
ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer
selection stored in the MUXn_SEL[3:0] fields. FIR data is stored LSB-justified, but shifted left by 9 bits.
2.2.7
Voltage References
A bandgap circuit provides the reference voltage to the ADC. The amplifier within the reference is chopper
stabilized, i.e., the chopper circuit can be enabled or disabled by the MPU using the I/O RAM control field
CHOP_E[1:0] (I/O RAM 0x2106[3:2]) . The two bits in the CHOP_E[1:0] field enable the MPU to operate the
chopper circuit in regular or inverted operation, or in toggling modes (recommended). When the
chopper circuit is toggled in between multiplexer cycles, dc offsets on VREF are automatically averaged
out, therefore the chopper circuit should always be configured for one of the toggling modes.
Since the VREF band-gap amplifier is chopper-stabilized, the dc offset voltage, which is the most
significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the
chopper circuit. Both the 71M6545/H and the 71M6xx3 feature chopper circuits for their respective VREF
voltage reference.
The general topology of a chopped amplifier is shown in Figure 6 . The CROSS signal is an internal on-
chip signal and is not accessible on any pin or register.
V inp
V inn
A
B
A
B
+
-
G
A
B
A
B
V outp
V outn
CROSS
Figure 6: General Topology of a Chopped Amplifier
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